Semiconductor devices typically include a plurality of circuits forming an integrated circuit. In an integrated circuit, the devices and elements formed in a semiconductor substrate are interconnected with metal leads (i.e., metal lines or interconnects) which are typically formed by sequential deposition, masking, and etching, generally referred to as metallization. Metallization starts in the masking area where small openings or windows, called vias or contacts, are etched through all the surface layers, down to the active regions of the devices. Following contact masking, a thin layer of conductive material is deposited by, for example, vacuum evaporation, sputtering, or chemical vapor deposition (CVD) techniques, over the entire wafer. The unwanted portions of this layer are removed by Chemical Mechanical Polishing (CMP). This step leaves the surface covered with thin lines of metals, that is interconnects.
The aforementioned process is described with reference to a single damascene structure (a single-level or single -layered metal structure). Increasing chip density has placed more components on the wafer surface which in turn has decreased the area available for surface wiring. Multi-level or multi-layered schemes such as dual damascene structures have become desirable to increase chip density. Typically, multi-level schemes start with a standard metallization process which leaves the surface components partially wired together. Next a layer of dielectric material such as oxide, silicon nitride, or polyimide is deposited thereon. The dielectric layer undergoes a masking step that etches contacts or vias down to a first level metal.
Metal has been employed to interconnect the electrical contacts formed between an overlying conductive region and an underlying region through a layer of dielectric material. Typically, the overlying layer is metal and the underlying layer may be a doped semiconductor region, salicide, or another metal layer. The contact between the two layers is through the conductive filled windows or openings, the contacts and vias described above. Contacts refer to an interconnect which interconnects a source-drain region, salicide or polysilicon to metal while vias refer to an interconnect which connects metal to metal.
Multi-level metal systems are more costly, of lower yield, and require greater attention to planarization of the wafer surface and intermediate layers to create good current-carrying leads. Thus, it is important to reduce the processing steps required to form multi-level structures.
According to prior art methods such as described in U.S. Pat. No. 4,789,648 to Chow et al. which is incorporated herein by reference, conductive material is deposited on a surface including an interconnect groove and inside the opening of the contact simultaneously. In particular, the Chow et al. patent discloses a method for forming interconnects on a single conductive layer including vias and wiring channels, referred to as interconnect grooves in a multi-layered system utilizing a blanket CVD technique. This is done to minimize the number of steps required to form the desired structure. However, there are several problems associated with these types of prior art techniques. For example, the conductive material often overhangs at the edge of the opening of the contact which creates voids or seams within the conductive material in the opening of the contact. More specifically, voids and seams typically result when growth of the conductive material in the interconnect grooves and on sidewalls of the contact or via holes occurs before growth of the conductive material at the bottom of the contact or via hole has been completed. The presence of seams and voids adversely affects the processing yield.
A method for selectively filling contacts or vias with CVD tungsten is known in the art as described in U.S. Pat. No. 4,987,099 to Flanner which is incorporated herein by reference. Selective CVD can be used in order to minimize processing steps such as additional etching and polishing required to remove excess conductive material deposited when using blanket CVD. However, when selective CVD as described in Flanner is used, the coverage of the conductive material may be incomplete causing voids and seams to appear in the contact. As noted, processing yield is negatively impacted by the presence of seams and voids.